====== The KU060rev.1 Board FMC Problem ======

===== Overview =====

Connectors J34 and J35 are incorrectly placed in the schematic, but net names were assigned consistently for each schematic page. In practice, this means that jack J34 is composed of pin columns A-D that were supposed to be assigned to connector "FMC1-CFG" (for ConfigMon/JCM) and E-K from "FMC2-SPARE". In turn J35 is composed of pin columns A-D that were supposed to be assigned to connector "FMC2-SPARE" and E-K from "FMC1-CFG" (for ConfigMon/JCM).

In other words:

J34 (labeled as FMC2 on the silkscreen) consists of
  * All MGTs intended for FMC1
  * banks A-D that are named FMC1 from power domain FMC1
  * banks E-K that are named FMC2 from power domain FMC2

J35 (labeled as FMC1 on the silkscreen) consists of
  * All MGTs intended for FMC2
  * banks A-D that are named FMC2 or MZ2 from power domain FMC2
  * banks E-K that are named FMC1 from power domain FMC1


==== Electrical Implications ====

If both FMC connectors on a KU060 Rev.1 card are used, then both operate in the same power domain. LA[x] pins and the IO-banks they are assigned to on the DUT-FPGA are mixed. On the FPGA side, the FMC-LA[x] pins of each FMC card are attached to multiple different IO-Banks on the FPGA, which are supplied from different KU060 power rails. In practice, all FMC-IOB bank power supply banana jacks now form one single power plane. See schematics for further information.

==== Design Implications ====

This mixed signal assignments for FMC cards implies additional FPGA design constraints. 
  * The functionality of FMC1 and FMC2 are inverted.
  * For MGT/DP[x] related signals, no further considerations are necessary, as all MGTs FMC1 are now routed to FMC2, and all MGTs from FMC2 are routed to FMC1.
  * The LA[x] pin array is composed of pins from different are IO banks, and therefore their IOBs on the FPGA fabric are quite far apart. However, LA pins are low-speed pins, so the practical impact on routability and timing is low.
  * Besides this, the incorrect signal placement on the connectors has caused certain traces to be routed "the long way around" the board, which means that their length is much different from that of the correctly placed signals. Also, certain differential pairs' trace length is not well matched, causing varying impedance and trace length between members of individual pairs.

===== Solution for future Revision Boards =====

Spin Revision 2+:
  * Reassign pins for columns A-D to the correct connector. 
  * Re-route the relevant signals, as they currently take very lengthy paths across the PCB to go to the "wrong" FMC receptacle
  * Other connect attached pins were verified manually through inspection by Christian and Gary, and should be OK.

===== Solution for Rev.1 Boards =====

There is a hardware fix FMC card designed by Christian M. Fuchs.

This is a dual-FMC module that occupies both FMC connectors on the KU060 DuT. It provides two correctly working and correctly assigned FMC connectors with clear indication of which connector serves what function. It also corrects some non-matching differential-pair trace length issues on the miss-routed LA[x] pins. It can be manufactured on demand, and it takes care of every aspect that has practical FPGA design and electrical implications.

{{:wiki:ku060_interposer.png?800| KU060 FMC Interposer Picture}}

===== Mitigation without Hardware Fix for Rev.1 Boards =====

Otherwise, Rev 1 boards still can be used correctly, but there are a few caveats. 
  * the now shared power domain for both FMC cards,
  * FPGA designs will be lightly impeded due to the 9 LA[x] diffential pairs being coming from different FPGA IO banks than intended. In most cases, this should not be an issue. 
  * J35 (ex-FMC1-CFG) gains several pins and MGTs which were not supplied to the the Config-FMC card. This makes ConfigMon/JCM implementation easier and allows more complex designs
  * J34 (ex-FMC2-SPARE) will have fewer usable pins, and most importantly, looses half of its MGTs
and:
  * Board documentation is actively misleading:
    * The net-names, schematics, and PCB design files mislead the designer, as the _MZ1, _FMC1,_MZ2,_FMC2 net names are ambiguous and do not correspond to the actual connectors on the board.
    * The role/purpose designation of FMC1 and FMC2 as "Config" and "Spare" is in practice swapped

To sanitize the Rev.1 board files at least optically:
  * On the board, mark J34 as FMC2/ConfigMon (place sticky label)

  * On the board, mark J35 as FMC1/Spare (place sticky label)

  * In the netlist and schematic change net-names as follows, then regenerate PCB design and export new netlist, schematic, PCB-design, gerbers, ODB++, DXF and send them to Christian and Gary for review.:
    * J34:
      * MGT_xxxxx_MZ1 to MGT_xxxxx_FMC2
      * B
        * CLK_DIR_FMC1 to CLK_DIR_FMC2
        * GBTCLK1_M2C_P_FMC1 to GBTCLK1_M2C_P_FMC2
        * GBTCLK1_M2C_N_FMC1 to GBTCLK1_M2C_N_FMC2
      * C
        * LA06_P_FMC1 to LA06_P_FMC2
        * LA06_N_FMC1 to LA06_N_FMC2
        * LA27_P_FMC1 to LA27_P_FMC2
        * LA27_N_FMC1 to LA27_N_FMC2
        * SCL_FMC1 to SCL_FMC2
        * SDA_FMC1 to SDA_FMC2
        * GA0_FMC1 to GA0_FMC2
      * D
        * PG_C2M_FMC1 to PG_C2M_FMC2
        * GBTCLK0_M2C_P_MZ1 to GBTCLK0_M2C_P_FMC2
        * GBTCLK0_M2C_N_MZ1 to GBTCLK0_M2C_N_FMC2
        * LA01_P_CC_FMC1 to LA01_P_CC_FMC2
        * LA01_N_CC_FMC1 to LA01_P_CC_FMC2
        * LA05_P_FMC1 to LA05_P_FMC2
        * LA05_N_FMC1 to LA05_N_FMC2
        * LA09_P_FMC1 to LA09_P_FMC2
        * LA09_N_FMC1 to LA09_N_FMC2
        * LA23_P_FMC1 to LA23_P_FMC2
        * LA23_N_FMC1 to LA23_N_FMC2
        * LA26_P_FMC1 to LA26_P_FMC2
        * LA26_N_FMC1 to LA26_N_FMC2
        * TDO_FMC1 to TDO_FMC2
        * TDI_FMC1 to TDI_FMC2
        * GA1_FMC1 to GA1_FMC2
      * E-K
        * do not change, they are consistent!
    * J35
      * MGT_xxxxx_MZ2 to MGT_xxxxx_FMC1
      * B
        * CLK_DIR_FMC2 to CLK_DIR_FMC1
      * C
        * LA06_P_FMC2 to LA06_P_FMC1
        * LA06_N_FMC2 to LA06_N_FMC1
        * LA10_P_FMC2 to LA10_P_FMC1
        * LA10_N_FMC2 to LA10_N_FMC1
        * LA14_P_FMC2 to LA14_P_FMC1
        * LA14_N_FMC2 to LA14_N_FMC1
        * LA18_P_CC_FMC2 to LA18_P_CC_FMC1
        * LA18_N_CC_FMC2 to LA18_N_CC_FMC1
        * LA27_P_FMC2 to LA27_P_FMC1
        * LA27_N_FMC2 to LA27_N_FMC1
        * SCL_FMC2 to SCL_FMC1
        * SDA_FMC2 to SDA_FMC1
        * GA0_FMC2 to GA0_FMC1
      * D
        * PG_C2M_FMC2 to PG_C2M_FMC1
        * BTCLK0_M2C_P_FMC2 to GBTCLK0_M2C_P_FMC1            << fixes also a typo
        * BTCLK0_M2C_N_FMC2 to GBTCLK0_M2C_N_FMC1            << fixes also a typo
        * LA01_P_CC_FMC2 to LA01_P_CC_FMC1
        * LA01_N_CC_FMC2 to LA01_P_CC_FMC1
        * LA05_P_FMC2 to LA05_P_FMC1
        * LA05_N_FMC2 to LA05_N_FMC1
        * LA09_P_FMC2 to LA09_P_FMC1
        * LA09_N_FMC2 to LA09_N_FMC1
        * LA13_P_FMC2 to LA13_P_FMC1
        * LA13_N_FMC2 to LA13_N_FMC1
        * LA17_P_CC_FMC2 to LA17_P_CC_FMC1
        * LA17_N_CC_FMC2 to LA17_N_CC_FMC1
        * LA23_P_FMC2 to LA23_P_FMC1
        * LA23_N_FMC2 to LA23_N_FMC1
        * LA26_P_FMC2 to LA26_P_FMC1
        * LA26_N_FMC2 to LA26_N_FMC1
        * TDI_FMC2 to TDI_FMC1
        * TDO_FMC2 to TDO_FMC1
        * GA1_FMC2 to GA1_FMC1
      * E-K
        * do not change, they are consistent!